The present invention relates generally to semiconductor technology, and more particularly, to a method for manufacturing a semiconductor device.
Due to high integration of semiconductor devices, the distance between conductive lines such as word lines has decreased; and therefore, the margin of a contact process has been reduced. In order to secure the margin of a contact process, a self-aligned contact (SAC) process is employed.
FIGS. 1A through 1H are cross-sectional views illustrating the processes, including an SAC process, of a conventional method for manufacturing a semiconductor device.
Referring to FIG. 1A, a gate insulation layer 11, a first polysilicon layer 12, a tungsten layer 13 and a hard mask nitride layer 14 are stacked on a substrate 10 which has a cell region CELL and a peripheral region PERI. Gates G are formed by patterning the hard mask nitride layer 14, the tungsten layer 13 and the first polysilicon layer 12 through a photolithographic process.
Next, a capping nitride layer 15 is formed along the profile of the entire surface including the gates G. An oxide-based first interlayer dielectric 16 is formed on the capping nitride layer 15.
Referring to FIG. 1B, the first interlayer dielectric 16 is CMPed (chemically mechanically polished) using an HSS (high selectivity slurry) having high etching selectivity of a nitride layer with respect to an oxide layer, such that portions of the capping nitride layer 15 on top of the gates G are exposed.
Referring to FIG. 1C, a mask pattern 17 is formed with an opening over a landing plug contact area, and landing plug contact holes 18 are defined by etching portions of the first interlayer dielectric 16 between the gates G using the mask pattern 17 as an etch mask.
At this time, in order to etch the first interlayer dielectric 16 formed between the gates G and having a substantial thickness, over-etching should be conducted. During the over-etching, top corner portions A of the hard mask nitride layer 14 are lost, so the hard mask nitride layer 14 has a non-uniform profile.
Referring to FIG. 1D, the mask pattern 17 is removed, and a buffer oxide layer 19 is formed on the entire surface.
The buffer oxide layer 19 is formed to a large thickness on both the gates G and the first interlayer dielectric 16, and is formed to a relatively small thickness on the bottoms of the landing plug contact holes 18.
The buffer oxide layer 19 functions to prevent the hard mask nitride layer 14 from being lost when subsequently conducting a process for removing portions of the capping nitride layer 15.
Referring to FIG. 1E, an entire surface etching process is conducted during which portions of the buffer oxide layer 19, the capping nitride layer 15, and the gate insulation layer 11 present on the bottoms of the landing plug contact holes 18 are removed to expose portions of the substrate 10.
While conducting the entire surface etching process, loss of the first interlayer dielectric 16 and the hard mask nitride layer 14 is prevented by the buffer oxide layer 19 which is formed on the gates G and the first interlayer dielectric 16 to a relatively large thickness.
Referring to FIG. 1F, the landing plug contact holes 18 are filled by forming a second polysilicon layer 20 on the entire surface of the resultant substrate 10.
Referring to FIG. 1G, by CMPing (chemically mechanically polishing) the second polysilicon layer 20, landing plug contacts 20A are formed in such a way as to be isolated in their respective landing plug contact holes 18.
At this time, in order to prevent an unwanted short caused by bridging of adjacent landing plug contacts 20A, the CMP is conducted to the height X1 (see FIG. 1F) so that portions of the hard mask nitride layer 14 which constitute the non-uniform profiles are substantially removed.
Referring to FIG. 1H, a second interlayer dielectric 21 is formed on the entire surface including the landing plug contacts 20A. Then, by patterning the second interlayer dielectric 21 in both the cell region CELL and the peripheral region PERI and the hard mask nitride layer 14 in the peripheral region PERI through a photolithographic process, a first contact hole, which exposes the landing plug contact 20A in the cell region CELL, and a second contact hole, which exposes the tungsten layer 13 in the peripheral region PERI, are defined. Thereafter, by filling a conductive layer in the first and second contact holes, a first contact plug 22, which is electrically connected to the substrate 10 in the cell region CELL, and a second contact plug 23, which is electrically connected to the tungsten layer 13 of the gate G formed in the peripheral region PERI, are formed.
The conventional method for manufacturing a semiconductor device has problems as described below.
First, the hard mask nitride layer 14 should be formed sufficiently thick in consideration of the thickness of the hard mask nitride layer 14 that will be lost when conducting the etching process for defining the landing plug contact holes 18 (see FIG. 1C) and the CMP process for forming the landing plug contacts 20A (see FIG. 1G). When the hard mask nitride layer 14 is formed thick, the aspect ratio of the gates G increases making it difficult to control the etch profile when etching the gates G. As a consequence, defects such as leaning of the gates G occur, and the line width of the gates G becomes non-uniform, whereby the resistance of the individual gates G vary depending upon the position of the gate G in a wafer, making it impossible to secure uniform characteristics of a semiconductor device.
Second, since the aspect ratio of the individual gates G increases, voids are likely to be produced in the first interlayer dielectric 16 which is filled between gates G in the cell region CELL in which a gap between the gates G is narrow. The second polysilicon layer 20 may then fill in the voids and cause a defect in which an adjacent landing plug contact 20A is short-circuited.
Third, in order to ensure that polishing is stopped at the position of the capping nitride layer 15 when conducting the CMPing process for the first interlayer dielectric 16 (see FIG. 1B), the HSS having high etching selectivity of a nitride layer with respect to an oxide layer should be used. In this regard, since the HSS is expensive in that it contains a ceria-based abrasive and a number of additives, the manufacturing cost of the semiconductor device increases.
Fourth, when conducting the CMP process for forming the landing plug contacts 20A (see FIG. 1G), in order to prevent adjacent landing plug contacts 20A from being bridged, the CMP process should be conducted to height X1 (see FIG. 1F) so as to remove the portions of the hard mask nitride layer 14 having non-uniform profiles. For this purpose, the hard mask nitride layer 14, the first interlayer dielectric 16 and the second polysilicon layer 20, which have different polishing rates, should be simultaneously polished. In this regard, as materials having different polishing rates are simultaneously polished, the process burden increases. Further, due to the differences in polishing rates among the materials to be polished, defects, such as dishing (see part B of FIG. 1G) in which the first interlayer dielectric 16 and the landing plug contacts 20A subside below the surface of the hard mask nitride layer 14, are likely to occur.
Fifth, since the thickness D1 of the hard mask nitride layer 14 in the peripheral region PERI is substantial, when conducting the etching process for defining the first and second contact holes (see FIG. 1H), the process burden increases due to a substantial difference in thickness between the layers to be etched in the cell region CELL and those in the peripheral region PERI.
Sixth, when defining the second contact hole in the peripheral region PERI (see FIG. 1H), if misalignment occurs between the second contact hole and the gate G, while the hard mask nitride layer 14 having the substantial thickness is etched, the first interlayer dielectric 16 on the side surface of the gate G is also etched causing a portion of the substrate 10 at a side of the gate G to be exposed directly below the second contact hole. Thus, as shown in the part C of FIG. 1H, defects are caused in that the second contact plug 23 filled in the second contact hole and the substrate 10 are likely to be short-circuited.